The present invention relates to a common-bus-type multiprocessor system and, more specifically, to a multiprocessor system in which system bus data is transferred in a packet form.
As shown in FIG. 17, in a conventional common-bus-type multiprocessor system, bus interfaces 5-8 respectively connected to processors 1-3 and a memory 4 share a single system bus 9. A clock signal 12 is provided from a clock circuit 11 to the respective bus interfaces 5-8, and only one bus interface that has acquired the use right of the system bus 9 according to a bus arbitration signal 10 can use the system bus 9, with one-clock period as the unit use time. That is, at a certain time instant, only one bus interface can use the system bus 9.
FIG. 18 shows a relationship between the clock signal 12 and data on the system bus 9. When, for instance, the processor 1 is using the system bus 9 during a certain clock of the clock signal 12, the other processors 2 and 3 cannot use the system bus 9 during that clock. Mark 1 FIG. 18 means that the bus interface 5, that is connected to the processor 1, is using the system bus 9.
When a plurality of bus interfaces that are connected to the system bus 9 request the use of the system bus 9 at the same time, the bus interfaces that have acquired the use right sequentially use the system bus 9 in the order of the use right acquisition. Therefore, when many bus interfaces issue bus-requests at the same time, there occur the problems of the need of waiting for data transfer and a small data quantity that can be transferred at a time. Further, intricate processes are required to implement the bus arbitration.